1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device which generates a refresh request signal to carry out a self-refresh when a refresh is needed.
2. Description of the Related Art
In a dynamic random access memory (DRAM) including a memory cell having a capacitor for retaining information, the information gradually fades away and vanishes due to a leakage of the charges in the capacitor as the time elapses. Accordingly, before the information vanishes, an operation by which the information is refreshed i.e., a refresh operation, must be carried out.
The refresh operation is based on a refresh request signal, which is usually generated by a central processing unit (CPU) provided outside the DRAM chip, or by a timer or a ring oscillator provided inside the chip. In either case, the refresh is carried out intermittently. In practice, a DRAM which can detect whether or not a refresh is needed and can carry out the refresh when the potential of the capacitor of the memory cell is changed to an extent such that a refresh is needed, has been proposed.
Where the DRAM carries out a self-refresh operation, the function thereof is equivalent to that of a static RAM (SRAM), from the aspect of a CPU outside the chip, although a problem of a conflict in the priority between a memory access and the refresh exists inside the chip. Accordingly, such a DRAM is referred to as a pseudo SRAM (PSRAM).
On the other hand, fluctuations in the time interval at which the refresh is needed are caused by the voltage, temperature, manufacturing process, e.g., amount of leakage in the capacitor, and the like. In the method where the refresh is periodically carried out, e.g., using a clock signal output by a timer, the refresh interval must be shortened (usually about 4 msec) to ensure that a destruction of the content of memory is prevented at all costs. Accordingly, the number of times a refresh operation is carried out is increased, resulting in an increase in the power dissipated and an increase in the number of times a conflict occurs between the refresh and the memory access. That is, the method where the refresh is periodically carried out irrespective of the timing at which a refresh is actually needed is not preferable.
Conversely, a method is known wherein the refresh is carried out at the timing at which a refresh is actually needed, based on a detection of the potential of the capacitor. In this method, the refresh interval can be lengthened as required, resulting in a decrease in the power dissipated and a decrease in the number of times a conflict occurs between the refresh and the memory access. In particular, the advantage of the former method is that it contributes to a battery back-up operation. The method of detecting the timing at which the refresh is needed is realized by an arrangement wherein a detecting capacitor having the same constitution as a capacitor of a memory cell is formed on a substrate, so that the voltage thereof can be detected, and the detecting capacitor is charged during the refresh operation, and when the voltage thereof falls below a predetermined value, the refresh request signal is generated.
In this case, the timing of the generation of the refresh request signal must be selected so that the correct read operation can be carried out even for a memory cell at which a leak first occurs among all of the memory cells. However, this can be changed depending on the characteristics of the substrate, i.e., the chip. Also, a problem arises in the selection of the location of the detecting capacitor on the substrate. Accordingly, conventional measurements have been taken whereby a plurality of detecting capacitors are connected via fuses and a desired capacitance is obtained by cutting the fuses by a laser beam so that a desired refresh timing is obtained in each chip.
However, obtaining the desired capacitance by cutting the fuses by a laser beam is difficult and cumbersome. Determining the desired value of the capacitance is also cumbersome, and further, if the same capacitance is selected for each chip, a sufficient margin must be assured. In this case, the refresh interval is shortened, and thus there is little difference between the method utilizing the detection of the potential of the capacitor and the method wherein the refresh is periodically carried out using an external clock.